1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing, and, more particularly, to the formation of an interconnect structure having a contact plug for directly contacting a circuit element.
2. Description of the Related Art
Semiconductor devices, such as advanced integrated circuits, typically contain a huge number of circuit elements, such as transistors, capacitors, resistors and the like, which are usually formed in a substantially planar configuration on an appropriate substrate having formed thereon a crystalline semiconductor layer. Due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements may generally not be established within the same level on which the circuit elements are manufactured, but require one or more additional “wiring” layers, which are also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, which are also referred to as “vias,” that are filled with an appropriate metal and provide the electrical connection between two neighboring stacked metallization layers.
Due to the continuous reduction of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is, the packing density, also increases, thereby requiring an even larger increase in the number of electrical connections to provide the desired circuit functionality. Therefore, the number of stacked metallization layers usually increases as the number of circuit elements per chip area becomes larger and/or the sizes of individual metal lines and vias, as well as the spacing in between, are reduced. Consequently, for advanced semiconductor devices, the connection of the circuit elements with the first or lowest metallization layer requires a sophisticated contact technology for manufacturing respective contact plugs, which directly connect to contact regions of circuit elements, such as drain/source regions, gate electrodes of transistors and the like. Thus, the contact plugs provide the electrical contact of the individual circuit elements to the first metallization layer, which is formed above an interlayer dielectric material that encloses and passivates the circuit elements.
During the formation of respective contact plugs, a plurality of complex processes are performed, including the deposition of dielectric materials, the planarization of the dielectrics, the etching of contact openings, several cleaning processes, the filling in of appropriate contact metals and the like, wherein certain problems may arise in a typical conventional process flow, as will be described in more detail with reference to FIGS. 1a-1d. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in an advanced manufacturing stage. The device 100 may comprise one or more circuit elements 103 formed above a substrate 101 comprising a semiconductor layer 102, such as a silicon layer. The circuit elements 103 may represent field effect transistors, capacitors and the like, wherein critical feature sizes, for instance a gate length of the circuit elements 103 when representing field effect transistors, may be in the range of approximately 100 nm and significantly less. In this manufacturing stage, a contact etch stop layer 104, for instance comprised of silicon nitride, may be formed so as to enclose the circuit elements 103, followed by an interlayer dielectric material 105, which may be comprised of silicon dioxide.
Typically, the device 100 may be formed on the basis of the following processes. The circuit elements 103 may be manufactured in accordance with well-established recipes including advanced lithography, deposition, etch, implantation, anneal techniques and the like. Thereafter, the contact etch stop layer 104 may be deposited on the basis of well-established plasma enhanced chemical vapor deposition (PECVD) techniques, wherein, in sophisticated applications, the layer 104 may be provided with a specific intrinsic stress in order to enhance the performance of at least some of the circuit elements 103. Thereafter, the interlayer dielectric material 105 may be deposited on the basis of high density plasma assisted chemical vapor deposition (CVD) techniques or any other appropriate deposition method, wherein, for instance, TEOS may be used as a precursor material in order to form silicon dioxide with required characteristics with respect to mechanical stability, moisture rejection and the like. Although a plurality of recipes are well established in the art in which the interlayer dielectric material 105 may be deposited in a substantially flow-like manner, a certain degree of non-uniformity of the finally obtained topography may be observed, which may adversely affect any subsequent processes, such as a photolithography for a subsequent patterning of the layers 105 and 104 in order to form respective contact plugs therein. Consequently, the surface topography of the device 100 may be planarized by advanced chemical mechanical polishing (CMP) techniques.
FIG. 1b schematically illustrates the semiconductor device after the planarization of the interlayer dielectric material 105 by means of CMP, thereby providing a substantially planar surface topography, wherein, however, a plurality of small cracks, scratches and other surface irregularities 106 may have been formed during the mechanical stress caused by the CMP process.
After the planarization of the layer 105, further processes may be performed on the basis of the surface topography as shown in FIG. 1b, wherein, for instance, a photolithography may be performed in order to provide a resist mask (not shown) on the basis of which respective contact openings are formed in the material 105. During this etch process, respective contact openings in the layer 105 may be formed to different depths, depending on the respective contact regions of the circuit elements 103, and hence the contact etch stop layer 104 is provided to reliably stop and control the previous etch process. Thereafter, the resist mask may be removed and a further etch process may be performed in order to open the contact etch stop layer 104. Subsequently, any further cleaning processes may be carried out in order to prepare the device for the deposition of appropriate barrier and metal materials for forming contact plugs in the layers 105 and 104. During many of these process steps, the scratches, cracks and surface irregularities 106 may be exposed to the respective reactive ambients of the various processes, thereby leading to a significant increase in size of the irregularities 106 in the lateral and/or the vertical direction. Consequently, during the subsequent filling in of barrier and metal material, the increased surface irregularities 106 may also be filled with a respective conductive material, which may have a negative impact on the further processing and finally on the device performance.
FIG. 1c schematically illustrates the device 100 in a further advanced manufacturing stage after the completion of the above-described process sequence. Hence, the device 100 may comprise a plurality of contact plugs 107, which may be filled with a highly conductive metal 108, such as tungsten and the like, wherein typically a barrier material 109 may be formed between the dielectric materials of the layers 105 and 104 and the highly conductive metal 108. Moreover, as previously explained, respective enlarged surface irregularities 106A may also be filled with the highly conductive material 108 and the barrier material 109, thereby providing a plurality of regions, which may affect the operational behavior of at least some of the circuit elements 103. For example, the respective contact openings and thus the enlarged surface irregularities 106A may be filled on the basis of well-established deposition techniques, such as sputter deposition for the barrier material 109 and CVD techniques for the highly conductive material 108, wherein any excess material thereof may afterwards be removed by CMP, which may additionally contribute to a lateral and vertical increase in size of the surface irregularities 106A, for instance by bridging neighboring metal-filled scratches. Consequently, at least some of the metal-filled surface irregularities 106A may take on a significant lateral dimension, which may result in the generation of non-desired conductive paths.
FIG. 1d schematically illustrates the device 100 in a further advanced manufacturing stage, wherein a metallization layer 110 is formed above the interlayer dielectric material 105. The metallization layer 110 may comprise a plurality of metal trenches or metal lines 112, which may contain a highly conductive metal 114, such as copper, aluminum and the like, wherein, in advanced applications including a highly conductive material, such as copper or copper alloys and the like, a respective barrier material 115 may be provided. The metal lines 112 may be formed in an appropriate dielectric layer 111, for instance comprised of silicon dioxide, fluorine-doped silicon dioxide, low-k dielectric materials and the like. The dielectric layer 111 may be formed on an etch stop layer or barrier layer 113, for instance comprised of silicon nitride, silicon carbide, nitrogen-enriched silicon carbide and the like. The metallization layer 110 may be formed on the basis of well-established inlaid or damascene techniques, in which respective openings such as trenches are formed in the dielectric layer 111 and the etch stop layer 113 followed by an appropriate fill process for forming the barrier layer 115 and providing the bulk material 114.
As previously explained, during the previous processes, the lateral extension of some of the surface irregularities 106A may have been increased so as to form a conductive path between two neighboring metal lines 112, as is for instance shown at 116. Consequently, an operational failure or at least a significantly increased leakage current may be observed, thereby possibly rendering the device 100 non-operational. Consequently, increased yield loss may be observed, in particular for highly sophisticated semiconductor devices, in which the reduced feature sizes of the circuit elements 103 may also require respective reduced dimensions of the metal lines 112 and of the respective spacings, thus even further increasing the risk of operational failures caused by metal-filled surface irregularities, such as the irregularities 106A.
In view of the situation described above, a need exists for an enhanced technique for the formation of contact plugs while avoiding or at least reducing the effects of one or more of the problems identified above.